Google Splits Its AI Chip. Here’s Why It Matters For Enterprises.
•InnovationEnterprise TechGoogle Splits Its AI Chip.
•Here’s Why It Matters For Enterprises.ByMaribel Lopez,Senior Contributor.Forbes contributors publish independent expert analyses and insights.
•I help firms understand AI, mobile and cloud to improve their businessFollow AuthorApr 22, 2026, 03:53pm EDT--:-- / --:--This voice experience is generated by AI.
هذا الخبر من Forbes. خبر يقدم أدوات ذكاء اصطناعي للتلخيص والترجمة والاستماع.
InnovationEnterprise TechGoogle Splits Its AI Chip. Here’s Why It Matters For Enterprises.ByMaribel Lopez,Senior Contributor.Forbes contributors publish independent expert analyses and insights. I help firms understand AI, mobile and cloud to improve their businessFollow AuthorApr 22, 2026, 03:53pm EDT--:-- / --:--This voice experience is generated by AI. Learn more.This voice experience is generated by AI. Learn more.Amin Vahdat, Google's SVP and Chief Technologist for AI Infrastructure, launches two new TPUsMaribel LopezThe AI chip acronym soup of CPUs, GPUs, TPUs, etc., shows how the computing landscape continued to expand and change over the past decade. At Google Cloud Next, the company released two distinct TPUs (Tensor Processing Units) instead of one — TPU-8t, built for training, and TPU-8i, built for inference and the emerging demands of agentic workloads. The launch highlights an architectural decision that reflects how AI workloads are diverging, with real implications for how enterprise buyers should think about AI infrastructure strategy.What Google Actually AnnouncedDuring a press and analyst session at Google Cloud Next, Amin Vahdat, Google’s SVP and Chief Technologist for AI Infrastructure, introduced the eighth-generation TPUs — and emphasized the plural intentionally. Vahdat said the two chips were designed from the ground up separately.TPU-8t is the training workhorse. Compared to last year's Ironwood generation, it delivers roughly three times the floating-point compute per pod, twice the network bandwidth per chip, and four times the bandwidth at scale-out — all with approximately the same pod size of 9,600 chips, but with denser, faster interconnects.TPU-8i is the inference and agent engine. It quadruples the pod size to 1,152 chips, delivers 10x the FP8 compute, 7x larger HBM memory capacity, and offers bidirectional scale-out bandwidth. The design priority is latency, not just throughput — a meaningful distinction as enterprises mov...المصدر: Forbes | Source: Forbes
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